Vivado is the IDE that is used for the "programming" of Xilinx FPGAs. Xilinx/AMD together with Altera/Intel are the two dominant vendors for FPGAs. Programming the device in this context means generating the configuration of the FPGA so that it implements some logic specified by the designer.

Vivado is a 70GB install and quite a piece of software. I'll try to give an orientation on how to use Vivado and give a high level conceptual and architectural overview of the system. Theand the work flows that are designed into the tools (and seem to have been widely adopted in the FPGA industry). There are many different ways for using Vivado but as I am a command line kind of person, I will of course look at how to script things as much as possible.

There is a lot of documentation that comes with Vivado. It does however seems to be well organized, which is nice. The large amount of docs can be pretty overwhelming though. I will try to break in down into understandable chunks here and Maybe It will help you as much reading it than it does it help me writing it.

Design Goals

The purpose of using vivado is to turn an Idea of a digital logic circuit in your head into something that is as close to actual hardware as it gets without needing to talk to chip foundries. It acheives this by building the configuration for an FPGA, a Field Programmable Gate Array. As the name suggests, an FPGA is a lage array of logic gates. The configuration file, aka bitstream, that is generated by Vivado does nothing other than interconnecting the logic gates to form the circuit that was described to Vivado using a hardware description language.

To be able to do this, Vivado needs to know about a few different aspects of the physical hardware device.

  • It most importantly needs to have a description of the circuit that is to be implemented. This is normally provided by the designer as a hirarchically organized set of files written in a hardware description language.
  • It needs to know about the connections to the outside world, that is which pin needs to be an input and which pin needs to be an output, what voltage levels they use and how they connect to the circuit inside the FPGA.
  • A set of timing contstraints that describe the requirements for the runtime behaviour (think operation frequency, etc) of the circuit.

The "Design Flow" of Vivado

Over the last few years, as more and more specialized circuits have been developed, Vivado has also learned a few new tricks. This is why in a current version of Vivado, there are many different ways to 'program' an FPGA. In the end though, it all boils down to essentially compiling the HDL into a device specific bistream.

  1. There is the classic register transfer level or RTL design flow, where the logic that should be implemented on the FPGA is described using a hardware description language like VHDL or Verilog and then these designs are integrated into the FPGA while taking into account the different constraints like pin selection and signal timings.
  2. There is HLS synthesis that takes C or C++ code as an input and tries to derive the needed logic description from that code. This has the benefit that the FPGA designer can think "algorithmically" and then Vivado takes on the task of translating the algorithm into a logic description. The downside is that the logic generated by Vivado may not be as efficient than human designed logic. This may though only be a temporary problem until the tooling gets sophisticated enough that the HLS code will only be slightly worse than its hand coded counterpart as it has with Assembly generation through compilers. The process here is essentially the same as before whith a transpilation step executed to generate the HDL, before then feeding it into the normal HDL pipeline.
  3. Model based design. This design flow takes mathematical models of systems (mostly signal analysis or control systems) as input and tries to generate logic to perform the transformations in the DSP/control pipelines. This design flow currently only works with tools from MathWorks like MATLAB or Simulink. This is really nice for the people that have lots of experience designing control and DSP algorithms using these tools, but is pretty much out of reach for any hobbyist, as these tools come with quite formidable license costs of their own. But as many companies do use these tools, this is of course a good business decision by Xilinx
  4. With the rise of 'AI', FPGAs have found another application in performing the calculations of the ML model directly in hardware. This speeds up the evaluation of a model by a lot and makes them a lot more energy efficient to run. As many ML models rely on the same Node/graph/weight paradyme, the people at Xilinx where able to develop tools that translate abstract model designs into Circuits that can be executed on the FPGA. For large networks this might also involve reconfiguring the FPGA on the fly to time multiplex neural nets onto the FPGA that would otherwise not fit.

As I am someone that likes to understand what I am doing and because I don't have a fancy license, I tend to focus on the RTL design flow. But the tools that try and transpile other kinds of descriptions are becoming better and better over time.

The IDE and other tools included in Vivado

Besides being a compiler for HDLs, Vivado integrates a host of other tools. There are a whole set of viewing tools that allow to view the layout of the circuit on the FPGA, among other things. There are tools for debugging the HDL description. There are tools that help with timing closure (the process of getting your circuit layed out in such a way that it meets the timing constraints), and a whole bunch of smaller utilities that help with documenting and reporting and other kinds of business paperwork.

Interesting for the hobbyist are the debugger/simulator and I personally do quite like taking a look at the finished layout on the chip.

Alternatives

I'd also like to mention that there is a lot of work on open source tools like yosys, verilator or GHDL for doing RTL design/simulation for FPGAs (and the simulation of course extends to any logic circuit). They have the benefit that they are a lot smaller and they allow you to take a look at how things work inside the tools and have the added bonus of no license headache. Vivado also really only runs on Ubuntu/RedHat linux distributions. I have gotten it to run on Fedora without much of a problem, but if you are not using one of those distros, that's another headache to deal with. The open source tools tend not to work for Xilinx/Altera FPGAs and focus more on FPGAs from Lattice. This is no real drawback for hobbyists as these chips are plenty powerful for hobbyists and smaller scale commercial applications. If you are however going to working with Xilinx ICs for professional reasons, there is really no way around Vivado.

Hope this was useful.